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1 October 1990 GaAs 800-mb/s serial communications chip set
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Abstract
A high-speed communications chip set based on a 1500-gate structured cell gate array, designed specifically for interprocessor communications in multiprocessor environments has been developed. Needing a minimum of support logic, these three chips provide all link functions, including parallel/serial and serial/parallel conversion, data encoding/decoding, idle/quiet line detection, data clock phase recovery, and link error indicators. The link clock rate is 1 GHz, supporting a data rate of 800 megabit/second.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kelvin G. Hickman "GaAs 800-mb/s serial communications chip set", Proc. SPIE 1291, Optical and Digital Gallium Arsenide Technologies for Signal Processing Applications, (1 October 1990); https://doi.org/10.1117/12.21015
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