Advanced packaging was applied during the early stages of CSWLP (Chip-Scale-Wafer-Level-Package) development for mainly package form-factor reduction. However, advanced packaging is used not only for package size reduction but also for many remarkable features including fan-out wafer level packages that are used for mobile application processor to increase interconnect counts and reduce chip height. 2.5D silicon interposer technology is also used for Graphics Processing Units (GPU) and Artificial Intelligence (AI) chips to interconnect System-on-Chips (SoC) and cache memory to provide wide bandwidth computing power. Advanced packaging will also play a key role in the upcoming Chiplet era. Canon developed our first i-line stepper for advanced packaging in 2011. Since then, we have expanded our tool lineup to support customer demands with developments supporting large size packages and panel-level packaging. In this paper, we compare advantages between wafer-level packaging and panel-level packaging. In addition, we study bonding error budgets for fine pitch bump package in the upcoming Chiplet era. We will compare bonding errors among Silicon interposers, Organic interposers, and Glass interposers and point out the importance of lithography tool distortion reduction to realize less than 10 µm bump pitch packages. Furthermore, we will report on our low distortion patterning solution, the FPA-5520iV LF2 advanced packaging stepper.
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