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Overlay control continues to be a critical aspect of successful semiconductor lithography processing, with overlay control systems becoming more and more elaborate to meet the requirements of advanced semiconductor nodes. Sampling optimization is especially important including the number of overlay measurements to perform on each wafer, the number of wafers to measure per lot, and where exactly to measure on each wafer. Conventional sampling optimization methodology is to collect dense data for a short period and use this data to optimize the locations to measure on the wafer. In recent years, rule-based sampling was introduced to relax this data requirement and improve the time to result. However, in both scenarios, one single sample plan is generated in offline optimization, which is then used in high volume manufacturing (HVM) without change, hence named “static sampling”. In this paper, we introduce a “dynamic sampling” approach, where multiple rule-based sample plans are generated, that complement each other by measuring different locations on the wafer, while meeting spatial and population balancing criteria. These sample plans can then be used in an alternating manner on a per-wafer basis (wafer-by-wafer dynamic sampling) and per-lot basis (lot-by-lot dynamic sampling) in HVM. In this paper, we first demonstrate the risks and the inherent trade-offs associated with static sampling by using overlay budget breakdown and best/worst case advanced process control (APC) simulations. We then characterize the overlay control improvement potential of dynamic sampling schemes through APC simulations using multiple metrics: on-product overlay, rework overlay and monitoring accuracy. Finally, we calculate the on-product overlay versus throughput cost function analysis and determine which dynamic sampling scheme is the most useful for which throughput conditions.
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