Solutions enabling advanced packaging and heterogeneous integration

Ken-Ichiro Mori; Douglas Shelton; Masaki Mizutani; Hiromi Suda; Ken-ichiro Shinoda; Seiya Miura

doi:10.1117/12.3032559

26 August 2024 Solutions enabling advanced packaging and heterogeneous integration

Ken-Ichiro Mori, Douglas Shelton, Masaki Mizutani, Hiromi Suda, Ken-ichiro Shinoda, Seiya Miura

Author Affiliations +

Proceedings Volume 13177, Photomask Japan 2024: XXX Symposium on Photomask and Next-Generation Lithography Mask Technology; 1317706 (2024) https://doi.org/10.1117/12.3032559
Event: Photomask Japan 2024, 2024, Yokohama, Japan

Abstract

In the initial stage of advanced packaging, it was applied to CSWLP (Chip-Scale-Wafer-Level-Package) mainly for the package form-factor reduction. However, advanced packaging is used not only for the package size reduction but also for many remarkable features including Fan-out wafer level packages that are used for mobile application processor to increase interconnect counts and reduce chip height. 2.5D silicon interposer technology is also used for Graphics Processing Units (GPU) and Artificial Intelligence (AI) chips to interconnect System-on-Chips (SoC) and cache memory to provide wide bandwidth. Advanced packaging will also play a key role in the upcoming heterogeneous integration. Canon developed the first i-line stepper for advanced packaging in 2011. Since then, we have expanded our tool lineup to support customer demands with developments supporting large size packages and panel-level packaging. In this paper, we compare advantages between wafer-level packaging and panel-level packaging. Furthermore, we will report our low distortion patterning solution of our latest packaging stepper, FPA-5520iV LF2 option.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Ken-Ichiro Mori, Douglas Shelton, Masaki Mizutani, Hiromi Suda, Ken-ichiro Shinoda, and Seiya Miura "Solutions enabling advanced packaging and heterogeneous integration", Proc. SPIE 13177, Photomask Japan 2024: XXX Symposium on Photomask and Next-Generation Lithography Mask Technology, 1317706 (26 August 2024); https://doi.org/10.1117/12.3032559

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KEYWORDS

Advanced packaging

Packaging

Reticles

Distortion

Optical lithography

Semiconductors

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