Paper
1 November 1990 Packaging of electronics for on- and off-FPA signal processing
Stuart N. Shanken
Author Affiliations +
Abstract
The process for manufacturing parallel processors using Z-plane technology is described along with the interconnectivity achievable for parallel processors. A thermal analysis performed on a typical module using the NASA SINDA model is shown. The Z-plane packaging technology producibility and reworkability are addressed.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stuart N. Shanken "Packaging of electronics for on- and off-FPA signal processing", Proc. SPIE 1339, Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array Technology II, (1 November 1990); https://doi.org/10.1117/12.23018
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KEYWORDS
Packaging

Parallel computing

Signal processing

Silicon

Electronics

Semiconducting wafers

Staring arrays

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