VLSI components for a 560-Mbit/s HDTV codec

Klaus Grueger; Peter Pirsch; Josef Kraus; Jochen Reimers

doi:10.1117/12.24226

1 September 1990 VLSI components for a 560-Mbit/s HDTV codec

Klaus Grueger, Peter Pirsch, Josef Kraus, Jochen Reimers

Proceedings Volume 1360, Visual Communications and Image Processing '90: Fifth in a Series; (1990) https://doi.org/10.1117/12.24226
Event: Visual Communications and Image Processing '90, 1990, Lausanne, Switzerland

Abstract

The hardware implementation of a DPCM coding algorithm with 2D prediction, noise shaping and fixed codeword length for the transmission of HDTV signals with 560 Mbit/s bit rate has been investigated. In order to reduce timing requirements an architecture with parallel processing elements and with modified DPCM-structure is proposed. DPCM and FIFO circuits as major components for such a codec have been designed for a VLSI-realization using 1.2|im CMOS technology.

Citation Download Citation

Klaus Grueger, Peter Pirsch, Josef Kraus, and Jochen Reimers "VLSI components for a 560-Mbit/s HDTV codec", Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); https://doi.org/10.1117/12.24226

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