Polysilicon etching for nanometer-scale features

Jean Lajzerowicz; Serge V. Tedesco; Christophe Pierrat; D. Muyard; M. C. Taccussel; Philippe Laporte

doi:10.1117/12.48916

1 March 1991 Polysilicon etching for nanometer-scale features

Jean Lajzerowicz, Serge V. Tedesco, Christophe Pierrat, D. Muyard, M. C. Taccussel, Philippe Laporte

Proceedings Volume 1392, Advanced Techniques for Integrated Circuit Processing; (1991) https://doi.org/10.1117/12.48916
Event: Processing Integration, 1990, Santa Clara, CA, United States

Abstract

Polysilicon etching is a critical process for VLSI. Recently1, HBr appeared to be the best choice for a good selectivity versus oxide and a good profile control. In this paper, we investigated a HBr-Cl2 chemistry in a classical RIE system at pressure below 15 Pa. The etching was performed with either resist or oxide masks. Results were optimized through statistical experimental designs. The influence of the different process parameters: power, pressure and gas flows were detailed. Etching of 100nm patterns, stopping within 70A thin gate oxide (even with a long overetch time) was achieved using the developped process.

Citation Download Citation

Jean Lajzerowicz, Serge V. Tedesco, Christophe Pierrat, D. Muyard, M. C. Taccussel, and Philippe Laporte "Polysilicon etching for nanometer-scale features", Proc. SPIE 1392, Advanced Techniques for Integrated Circuit Processing, (1 March 1991); https://doi.org/10.1117/12.48916

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