ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

David S. Rosky; Bruce H. Coy; Marc D. Friedmann

doi:10.1117/12.134921

1 March 1992 ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

David S. Rosky, Bruce H. Coy, Marc D. Friedmann

Author Affiliations +

Proceedings Volume 1577, High-Speed Fiber Networks and Channels; (1992) https://doi.org/10.1117/12.134921
Event: OE Fiber, 1991, Boston, MA, United States

Abstract

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

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David S. Rosky, Bruce H. Coy, and Marc D. Friedmann "ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications", Proc. SPIE 1577, High-Speed Fiber Networks and Channels, (1 March 1992); https://doi.org/10.1117/12.134921

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