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12 August 1992 256(V) x 256(H) full-frame area-array image sensor with on-chip electronics
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Proceedings Volume 1656, High-Resolution Sensors and Hybrid Systems; (1992) https://doi.org/10.1117/12.135932
Event: SPIE/IS&T 1992 Symposium on Electronic Imaging: Science and Technology, 1992, San Jose, CA, United States
Abstract
- A 256 x 256 pixel full frame CCDimage sensor has been developed that incorporates on-chip d. c. bias generation and clocking. Using a small pixel pitch of 10 im (V) by 10 im (H) these features allow the array to be packaged into very small dimensions with a total pin count of seven pins. By virtue of the three phase architecture the full well storage capacity can be increased with surface channel operation maximizing resolution under conditions of low scene contrast. In addition a modified technique of surface recombination is used to provide blooming suppression. Together these features make it well suited for applications which require a high performance miniature sensor. I.
© (1992) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stephen J. Strunk, William D. Washkurak, Savvas G. Chamberlain, and S. J. Hood "256(V) x 256(H) full-frame area-array image sensor with on-chip electronics", Proc. SPIE 1656, High-Resolution Sensors and Hybrid Systems, (12 August 1992); https://doi.org/10.1117/12.135932
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