Search for an effective methodology practical in IC manufacturing process development led to trial of quantitative 'concept selection' methodology in selecting the 'best' alternative for interlevel dielectric (ILD) processes. A cross-functional team selected multi-criteria with scoring guidelines to be used in the definition of the 'best'. The project was targeted for the 3 level metal backend process for sub-micron gate array product. The outcome of the project showed that the maturity of the alternatives has strong influence on the scores, because scores on the adopted criteria such as yield, reliability and maturity will depend on the maturity of a particular process. At the same time, the project took longer than expected since it required data for the multiple criteria. These observations suggest that adopting a simpler procedure that can analyze total inherent controllability of a process would be more effective. The methodology of the DFS (design for simplicity) tools used in analyzing the manufacturability of such electronics products as computers, phones and other consumer electronics products could be used as an 'analogy' in constructing an evaluation method for IC processes that produce devices used in those electronics products. This could be done by focusing on the basic process operation elements rather than the layers that are being built.

In order to lower manufacturing costs and increase performance, static random access memory (SRAM) bit cells are scaled progressively toward submicron geometries. The reliability of an SRAM is highly dependent on the bit cell stability. Smaller memory cells with less capacitance and restoring current make the array more susceptible to failures from defectivity, alpha hits, and other instabilities and leakage mechanisms. Improving long term reliability while migrating to higher density devices makes the task of building in and improving reliability increasingly difficult. Reliability requirements for high density SRAMs are very demanding with failure rates of less than 100 failures per billion device hours (100 FITs) being a common criteria. Design techniques for increasing bit cell stability and manufacturability must be implemented in order to build in this level of reliability. Several types of analyses are performed to benchmark the performance of the SRAM device. Examples of these analysis techniques which are presented here include DC parametric measurements of test structures, functional bit mapping of the circuit used to characterize the entire distribution of bits, electrical microprobing of weak and/or failing bits, and system and accelerated soft error rate measurements. These tests allow process and design improvements to be evaluated prior to implementation on the final product. These results are used to provide comprehensive bit cell characterization which can then be compared to device models and adjusted accordingly to provide optimized cell stability versus cell size for a particular technology. The result is designed in reliability which can be accomplished during the early stages of product development.

MOSFET instabilities as a result of plasma processing have received significant attention in recent years. The focus of previous research has been directed at basic MOSFET devices. This paper describes the effects of PECVD PSG passivation on EEPROM device reliability through the use of response surface methodology (RSM). The investigation produced evidence of hydrogen induced EEPROM device degradation. An activation energy of 0.41 eV has been calculated using array cycling data at temperatures between 85 degree(s)C and 125 degree(s)C. The use of FTIR analysis produced excellent correlation between accelerated electron/hold trapping and the Si-H content of the as-deposited film. This result demonstrates that FTIR measurements serve as an effective process monitor of hydrogen induced degradation. The effects of PECVD process parameters on film integrity have been evaluated through the utilization of a passivation integrity etch. The process window has been found to be bounded by poor write/erase characteristics at high Si-H levels and poor film integrity at very low Si-H levels in the as-deposited film.

Continual improvements in yield, reliability and manufacturability measure a fab and ultimately result in Total Customer Satisfaction. A new organizational and technical methodology for continuous defect reduction has been established in a formal feedback loop, which relies on yield and reliability, failed bit map analysis, analytical tools, inline monitoring, cross functional teams and a defect engineering group. The strategy requires the fastest detection, identification and implementation of possible corrective actions. Feedback cycle time is minimized at all points to improve yield and reliability and reduce costs, essential for competitiveness in the memory business. Payoff was a 9.4X reduction in defectivity and a 6.2X improvement in reliability of 256 K fast SRAMs over 20 months.

Defects that occur during wafer manufacturing are the cause of extrinsic reliability failures. A major challenge of building-in product reliability is finding and eliminating the causes of defects as efficiently as possible. One approach to this problem is to use automatic patterned wafer inspection equipment to locate wafers in-process that have non-random patterns of defective die. Information leading to the identification of assignable causes of defects or contamination can be obtained by analyzing such wafers. A method for estimating the number of non-random defective die per wafer is described. The method is based on the failure of Poisson statistics to provide an accurate estimate of the observed visual yield if defects fall in systematic or clustered arrangements. An example is given in which this approach resulted in processing improvements that produced a two-fold reduction in product defect density during a ten week period.

Snake/comb defect test structures and an in-line patterned wafer inspection system (Inspex) are very effective for monitoring, investigating, and controlling contamination in modern silicon wafer manufacturing. These techniques have been widely used in our wafer fabrication facility to monitor silicon wafer processing, and to diagnose device failures. In this paper, the methodology of using these techniques to evaluate and control Ti/TiN barrier layer particles is demonstrated. The correlation between these two techniques was studied. A defectivity control baseline for Ti/TiN deposition process was established using statistical analysis. New and improved preventative maintenance procedures were implemented based on the data from snake and Inspex monitors. As a result, the particle defectivity of the Ti/TiN sputtering process has been dramatically reduced in the Ti/TiN process. The column failures of BiCMOS fast SRAM devices have been reduced by approximately 30%, and the probe yield of the SRAM product line has increased by over 14%.

As device technology continues to push for larger scale integration defect reduction has become increasingly important for the manufacturability and reliability of ICs. In Bell Labs' Device Development Line, defect reduction in the resist apply area has been implemented through several means: (1) The development of reliable particle checks using a Surfscan 4500 as a process monitor involved solving wafer related problems as well as changes in our cleaning procedures which has reduced average number of particles/wafer. (2) Involvement in a Defect Reduction task force provided a method for electrically testing grid structures to determine statistical differences in possible sources of resist particles. This resulted in a process change which reduced the defect density tested at our first level of metallization. (3) The employment of a monochromatic light source provided a fast and efficient method of detecting cosmetic defects associated with the application of photoresist. This was particularly useful in the testing necessary to determine the root causes of these problems, and as a process monitor to insure the absence of these defects after their solutions were implemented. In this paper we will detail these sources of photoresist defects, and our solutions which helped to make state of the art technology manufacturable with improved reliability.

Aluminum is one of the main materials used in semiconductor manufacturing. It provides conductive interconnection lines for the device so that signals can be transmitted throughout the device. Any defects existing in this layer can cause interruption of the signal. Reducing the number of these defects is crucial for device yield improvement and circuit performance. With the INSPEX pattern wafer inspection system, a killer defect was located in our aluminum sputter process. Through a systematic approach, it was confirmed that the transfer of wafers from the production cassette to/from the sputter cassette produced aluminum contaminants on the wafer. These contaminants originated from the silicon wafer scraping the aluminum cassette groove and produced various sizes of aluminum particulates on the wafer surface. These contaminants were carried to the following patterning process and causes bridging and/or broken aluminum lines. After the defect source had been isolated, an automatic wafer transfer system was recommended for proper wafer handling. Now this defect has been eliminated. This study shows that in process development it is important to consider all possible contamination sources for total defect reduction.

A new multilevel metal failure mechanism is presented in the context of improved manufacturing and reliability. Device failures, with electrical overstress (EOS) characteristics, are shown to be caused by metal-to-metal shorts. These shorts occur when lower metal extrudes through vias and creates upper layer metal protrusions. The metal protrusions can produce immediate or time dependent shorts to closely spaced adjacent metal lines. The metal migration that forms the protrusion failures is unrelated to classical electromigration. This mechanism is unique in that the physical stresses associated with the fabrication process/materials dominates the creation of these protrusions and failures happen without any significant component of electromigration. Effects of stresses from fabrication will be discussed including: sintering conditions, interlevel dielectric properties, and metal system composition. Reliability studies are shown to support the theory that the accelerated lifetest failures from this mechanism occur when a thin oxide breaks down between the protrusion and its adjacent metal line.

As the VLSI/ULSI device density is increasing, the number of interconnects also increases at a much larger scale. Consequently, more interconnect related failures are expectedly threatening the quality and reliability of the devices. However, with an appropriate methodology, manufacturing defects can be removed from the source, thus preventing any latent field failures. This approach requires a total teamwork between various engineering groups: failure analysis, test/product engineering, manufacturing, etc. The purpose of this paper is to demonstrate a proven success of the 'Upstream Approach': A direct and effective methodology in preventing process-induced failures.

The understanding of failure mechanisms causing yield loss continues to be important when guaranteeing the reliability of a device to the customer. As vertical integration has increased and the horizontal geometries decreased in VLSI devices, the investigation of failure mechanisms has become increasingly more difficult. It has become necessary to incorporate more advanced equipment and techniques in the analysis of these failures. This investigation is an effort to understand the physical defect(s) related to a timing parameter sensitivity of a one megabit DRAM. These defects are primarily observed on repaired devices which have degraded such that they induce failures beyond the area of repair. This paper will provide an explanation of how the defect can effect the internal operation of the device and how this defect can degrade with time or be accelerated with reliability stressing. Advanced equipment such as a Focused Ion Beam system (FIB) and a Transmission Electron Microscope (TEM) were essential for precise milling, high magnification imaging, and elemental analysis capabilities. An advanced technique called SAXTEM (specific area TEM cross section) was also necessary in the analysis of the failure mechanism. Finally, corrective actions which will prevent the occurrence of this problem will be specified.

As minimum feature sizes are reduced in MOS silicon devices, dielectric breakdown continues to pose a formidable challenge. A more complete understanding of the failure mechanism which induces oxide rupture has become an absolute necessity in order to meet the advancing yield and reliability requirements of today's complex integrated structures. This paper will present an interesting insight into the nature of dielectric breakdown in MOS transistors produced from a novel cross-sectioning TEM sample preparation method using a focused ion beam tool. By using deductive failure analysis, it was possible to determine the location of the leakage within a 1000 angstroms portion of the transfer gate of a one megabit DRAM. Once localized, a creative combination of conventional glass lapping and focused ion beam techniques were used to produce the thin TEM slice which contained the oxide breakdown. An image of the breakdown was then obtained on a 200 keV TEM. Interestingly, the image revealed that the origin of the breakdown was associated with imperfections in the form of voids in the surface of the silicon substrate. These results proved to be consistent over multiple samples. In this paper a complete description of these images will be presented along with possible theories describing the fundamental origin of these defects.

The development of a metallization process with optical resistance to electromigration is, by nature, an iterative process. Accelerated stressing of metal test patterns allow quantitative comparison of the electromigration performance of metal fabricated with experimental processes. Understanding of structural differences between process alternatives can be enhanced by physical characterization of unstressed samples. Failure analysis of stressed structures provides insight into the relationship of these differences to the physical failure mechanisms. The analyses which identified process modifications to achieve improved electromigration performance are discussed.

This paper presents a perspective on the use of Wafer Level Reliability (WLR) in developing a competitive quality/reliability program. WLR is defined as accelerated stressing of test structures at the wafer level. The pros and cons of WLR are considered in five application areas: process control; qualification; benchmarking; reliability monitoring/prediction; and modeling. WLR examples are discussed in the areas of oxide breakdown, hot carrier degradation, and electromigration. The need to develop physical, statistical, and geometrical models to extrapolate from WLR results to actual products is discussed.

Electro-State Discharge (ESD) induced leakage in output transistors is a serious concern in modern CMOS processes. Previous papers have attributed an increase in output leakage after Human Body Model (HBM) ESD testing, to the formation of small silicon melt filaments in the drain of output N-channel transistors. These filaments are apparently caused by current localization and thermal runaway at the drain of the output transistor when driven too far into parasitic bipolar breakdown by an ESD pulse. In this paper, an in depth analysis of the melt filament related leakage characteristics, as well as physical failure analysis utilizing the techniques of Specific Area Cross-section Transmission Electron Microscopy (SAXTEM) was performed. With HBM stressing in the range 500 V to 6000 V, the induced leakage rarely exceeded the maximum specified device leakage current, but was observed to vary widely at a given stress voltage. With this wide leakage distribution it was shown that the measured threshold failure voltage depended on both the failure criteria for leakage during testing, and the sample size tested. This could significantly impact reliability testing and prediction. In addition, the stressed devices were observed to undergo a temperature dependent partial leakage recovery with time. Physical failure analysis was performed on leaking outputs in order to gain more insight into the actual mechanism responsible for the leakage. A Focused Ion Beam tool (FIB) was used to prepare thin cross sections containing the localized damaged regions. TEM analysis revealed silicon melt filaments, less than 100 angstroms thick, at the Si-SiO₂ interface above the LDD portion of the drain. Larger regions of heat damaged silicon were evident at both ends of these filaments. This may be the first application of TEM analysis to investigate ESD induced melt filaments in silicon. By using this technique as opposed to more conventional approaches it was possible to clearly image the damaged regions and gain greater insight into the nature of the mechanisms responsible.

Charge-Induced Voltage Alteration (CIVA) is a new scanning electron microscopy technique to rapidly localize open conductors on integrated circuits (ICs). CIVA uses a constant current source to power the IC under test and produces an image by monitoring the variation in voltage supplied to the IC as a function of electron beam position. This concept of observing supply voltage changes as in CIVA has been applied to Tunneling Current Microscopy (TCM). TCM has been used to localize oxide defects in biased, large area MOS capacitors before oxide breakdown by measuring the fluctuations in current with electron beam position. These changes are normally on the order of 10 nA. Conventional current amplifiers normally limit the applied voltage thereby reducing the operational range of the TCM technique unless special circuit modifications are employed. By using a constant current source and monitoring the voltage changes across the capacitor being analyzed, there are no voltage limitations. Signal magnitudes on the order of 5 mV have been recorded from capacitor defects using the CIVA setup. A detailed description of the CIVA acquisition system used for TCM and a comparison with conventional TCM are provided. Images of oxide defects before breakdown are presented to show that, while the two approaches are comparable and each has its own strengths and weaknesses, the CIVA approach is a superior technique for precursor localization.

We have studied the effects of gate etching on the threshold voltage of submicron, N-poly gate CMOS devices through etch processing in selected advanced commercial etchers using a variety of etching chemistries. We found that the threshold voltage of the P-channel (buried channel) transistors is very sensitive to the etched profile of the gate. In the cases of reentrant and/or notched profiles, a reverse short channel phenomenon was observed. However, the etched profile has little effect on the threshold voltage of the N-channel transistors. A model is proposed to explain the mechanism of the reverse short channel phenomenon. Cross-sectional SEM and electrical measurements are used to support the model. The impact of this reverse short channel phenomenon on manufacturability and reliability for buried channel devices is also discussed.

A unique statistical approach to hot-carrier lifetime estimates is proposed. Unlike previous work, this approach emphasizes the inherent variability in IC processing. As a result, log- normal distributions of hot-carrier lifetimes in micron and submicron n-channel MOS transistors are presented for the first time. It is also shown that the variation in these distributions can be independent of stress voltage. Therefore, accelerated voltage tests can be used to quickly gather statistical data. Without this statistical information, conventional lifetime techniques significantly overestimate the hot-carrier lifetime.

The effects of several key wafer processing conditions on submicron n-channel MOS transistor hot-carrier injection stability have been studied. Specifically, the interactions of gate oxide interface integrity, lightly doped drain spacer length and ion implant parameters, polycrystalline silicon gate oxidation sequence, and source-drain ion implant and anneal conditions have been examined. After wafer fabrication, packaged test transistors were subjected to accelerated hot-carrier stress conditions. Hot-carrier injection damage was assessed by measuring and comparing critical transistor DC parameters before and after stress. The relative impact of hot-carrier generation and trapping efficiency on the degradation of linear regime drain current was analyzed and compared for each set of process conditions. Additionally, circuit parameters were examined to assess the impact of process and device modifications on performance. Finally, an optimum set of processing conditions have been identified which insure maximum device stability without compromising device or circuit performance.

The fully depleted silicon-on-insulator (SOI) MOSFET is a candidate for deep-submicron VLSI due to the numerous advantages over bulk silicon devices, including resistance to short- channel effects, reduced parasitic capacitances, improved subthreshold slope, and higher transconductance. However, these devices can exhibit a low source-drain breakdown voltage, which is a result of the triggering of the parasitic bipolar transistor. The breakdown voltage in fully depleted SOI MOSFET's has been studied as a function of both silicon film thickness and channel length. In the long-channel regime (> 2 micrometers ), the breakdown voltage is found to decrease as film thickness is decreased. This is attributed to increasing lateral electric fields as film thickness decreases. As channel lengths are reduced, however, the ultra-thin devices eventually exhibit higher breakdown voltages than the thicker devices. The higher breakdown voltage in the ultra-thin devices is attributed to improved resistance to punchthrough and charging effects. As the channel length is reduced, there is a transition from a bipolar-dominated breakdown regime to a punchthrough-dominated regime. The channel length at which punchthrough becomes significant is greater in thicker films, resulting in lower breakdown voltages at deep-submicron channel lengths. Therefore, ultra-thin films may be preferred over thicker SOI for deep-submicron VLSI.

Silicon on sapphire (SOS) MOSFETs are light hole devices. Hot carrier induced degradation of SOS FETs are found to correlate with both substrate and gate currents. DC stressing experiments show that the effects of hot light holes are mainly charge trapping, and cause very little interface state generation. At gate biases that give rise to mixed carrier stressing, interface states are created in significant quantities. Mechanisms of hot carrier degradation in light hole devices are found to be consistent with those proposed for bulk silicon devices.

The conventional hydrogen-contained plasma etching for emitter via hole opening can introduce atomic hydrogen into poly emitter. After short time forward current stress, p-n-p transistors fabricated by this process show increase of both current gain ((beta) ) and base current 1/f noise in the median bias region. The subsequent low temperature annealing characteristics of p-n-p indicate that hydrogen boron pairs are dissociated. The (beta) increase during current stress can be explained by the reduction of effective surface recombination velocity of emitter due to hydrogen boron pair formation.

Hot carrier device lifetime diminishes dramatically as operating temperature decreases. The hot carrier lifetime at liquid nitrogen temperature is usually several orders of magnitude lower than at room temperature. In this work, we show the dependence of hot carrier device lifetime of LDD nMOSFETs on temperature and stress condition in the temperature range from 78 K to room temperature. There is a cross-over point at which the worst-case hot carrier stress condition switches from V_g approximately equals 1/2 V_d (V_g I_bmax) to V_g equals V_d with decreasing temperature. Consequently, the dominant damage mechanism switches from interface state generation to trapped charge generation.

Hot-carrier stressing has been shown to degrade hydrogen-passivated p-channel polysilicon-on- oxide MOSFETs by two parallel degradation mechanisms. We observe hot-carrier-induced degradation of hydrogen passivation at grain boundaries through the creation of additional donor-type grain boundary states in the channel, as well as hot-electron trapping in the gate oxide. Due to the presence of both of these degradation mechanisms, p-channel polysilicon MOSFETs exhibit anomalous hot-carrier-induced degradation behavior that has not been observed in bulk p-MOSFETs.

Under large voltage bias, the polysilicon thin film resistor can be switched to a 'short' state having resistance reduction by a factor of more than 100. In this paper, we will characterize an irreversible resistance transition in boron doped LPCVD polysilicon thin film resistors. The experimental results describing the effect of doping concentration, polysilicon film thickness and device dimensions on the resistance transition phenomena will be given. Also, the results of reliability testing will be reported.