Semi-integrated SOG/TEOS etchback process for multimetal submicron devices

Nadia Iazzi; Luca Zanotti; Laura Bacci; Patrizia Vasquez

doi:10.1117/12.142938

16 April 1993 Semi-integrated SOG/TEOS etchback process for multimetal submicron devices

Nadia Iazzi, Luca Zanotti, Laura Bacci, Patrizia Vasquez

Proceedings Volume 1803, Advanced Techniques for Integrated Circuit Processing II; (1993) https://doi.org/10.1117/12.142938
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States

Abstract

A semi-integrated SOG/TEOS planarization process for intermetal dielectric (ILD) has been developed in the CVD cluster system Precision 5000 (Applied Materials). The process consists of SOG etch back performed in one chamber immediately followed by plasma TEOS deposition in another chamber of the system, to reduce particle contamination and moisture adsorption in the SOG film. The main goal of the work was to develop an etchback process with very low SOG/TEOS selectivity (i.e., 0.7:1) and good etch uniformity, suitable for VLSI planarization requirements. The results of the parametric process characterization performed with the CHF₃/CF₄/Ar chemistry and the very satisfactory defectivity levels obtained for interconnections and intermetal oxide, for contacts leakage and capacitor breakdown are reported. Special emphasis has been devoted to the study of the oxide interface after the etchback to correlate the probable surface modification to the `peeling' effect evidenced on the TEOS film. The advantages of using Ar sputter to solve the adhesion problem are then discussed.

Citation Download Citation

Nadia Iazzi, Luca Zanotti, Laura Bacci, and Patrizia Vasquez "Semi-integrated SOG/TEOS etchback process for multimetal submicron devices", Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); https://doi.org/10.1117/12.142938

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