Technological limitations in submicron on-chip interconnect

Soo-Young Oh; Keh-Jeng Chang; Norman Chang; Ken Lee; John L. Moll

doi:10.1117/12.145475

21 May 1993 Technological limitations in submicron on-chip interconnect

Soo-Young Oh, Keh-Jeng Chang, Norman Chang, Ken Lee, John L. Moll

Proceedings Volume 1805, Submicrometer Metallization: Challenges, Opportunities, and Limitations; (1993) https://doi.org/10.1117/12.145475
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States

Abstract

The trend of the performance degradations, noise and reliability issues and their potential solutions are analyzed for the submicron ULSI interconnect lines. To analyze these submicron interconnect lines, a new paradigm (HIVE) for fast and accurate 2-D and 3-D interconnect capacitances and resistances calculation is developed. The analysis, using these interconnect parameters for HIVE, shows that a copper (Cu) line will improve the electromigrations, but not the interconnect delay and cross-talk noise significantly. The low temperature operation improve the interconnect delay and electromigration, but it increases the cost of system packaging. The optimum approach will be the combination of additional layers of non-scaled metal lines in a higher level, low permittivity interlevel dielectric, and the use of repeaters to maximize the performance, noise and reliability and to minimize the risk and cost.

Citation Download Citation

Soo-Young Oh, Keh-Jeng Chang, Norman Chang, Ken Lee, and John L. Moll "Technological limitations in submicron on-chip interconnect", Proc. SPIE 1805, Submicrometer Metallization: Challenges, Opportunities, and Limitations, (21 May 1993); https://doi.org/10.1117/12.145475

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KEYWORDS

Capacitance

Aluminum

Copper

Metals

Reliability

Resistance

Dielectrics

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