High-speed binary-image processor for reduction conversion and image rotation

Hiroyuki Matsumoto; Ikuro Oyaizu

doi:10.1117/12.131375

1 November 1992 High-speed binary-image processor for reduction conversion and image rotation

Hiroyuki Matsumoto, Ikuro Oyaizu

Proceedings Volume 1818, Visual Communications and Image Processing '92; (1992) https://doi.org/10.1117/12.131375
Event: Applications in Optical Science and Engineering, 1992, Boston, MA, United States

Abstract

A high-speed binary-image processor has been developed to perform reduction conversion while suppressing image degradation. The processor adopts two newly developed reduction- conversion methods: thin-line preservation reduction and multilevel display reduction, and also incorporates a 90-degree rotation function indispensable to image processing. For A4-size image data having a resolution of 200 dpi, the processor performs 1/3 reduction in 95 msec and rotation by 90 degrees in 66 msec.

Citation Download Citation

Hiroyuki Matsumoto and Ikuro Oyaizu "High-speed binary-image processor for reduction conversion and image rotation", Proc. SPIE 1818, Visual Communications and Image Processing '92, (1 November 1992); https://doi.org/10.1117/12.131375

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