Sub-0.5-um polysilicon etching on a MERIE system: a case study in manufacturing

Steve W. Swan; Graham W. Hills

doi:10.1117/12.167337

15 February 1994 Sub-0.5-μm polysilicon etching on a MERIE system: a case study in manufacturing

Steve W. Swan, Graham W. Hills

Proceedings Volume 2091, Microelectronic Processes, Sensors, and Controls; (1994) https://doi.org/10.1117/12.167337
Event: Microelectronic Processing '93, 1993, Monterey, CA, United States

Abstract

A polysilicon etch process designed for use in manufacturing must yield stable results for critical dimensions, line profile, gate oxide loss, gate oxide damage, defect density, and throughput; all of which must meet the desired specifications for the device being fabricated. A process that meets these requirements has been developed for undoped polysilicon with nominal linewidth of 0.45 micrometers and gate dielectric thickness of 90 angstroms on a single wafer (150 mm) magnetically enhanced reactive ion etch (MERIE) system. The impact of plasma induced charging on device performance is discussed using test results of time dependent dielectric breakdown for structures with polysilicon: gate antenna ratios in the range of 1:1 to 10,000.

Citation Download Citation

Steve W. Swan and Graham W. Hills "Sub-0.5-μm polysilicon etching on a MERIE system: a case study in manufacturing", Proc. SPIE 2091, Microelectronic Processes, Sensors, and Controls, (15 February 1994); https://doi.org/10.1117/12.167337

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