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9 June 1994 Design of a real-time high-quality SAR processor
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Research at the DRA, Malvern, has resulted in a series of algorithms which are capable of yielding focused, undistorted SAR imagery. Unfortunately these can only be implemented in a fraction of a percent of real-time on a standard work-station. In parallel with the algorithm development, therefore, has been research into a real-time implementation on a parallel computer (the Meiko CS1). This paper outlines the principles behind the software architecture design to achieve the desired speed. Processing functions considered include: initial motion compensation (based on accelerometer data), autofocus with phase correction, final processing and an intensity segmentation stage. Real time processing rates of about 10 MBytes/s are now routinely achieved. We indicate the compromises between processor power, available local memory and communications bandwidth needed to achieve real-time operation. Detailed timings derived from the implementation will be presented together with a discussion of the manner in which this could be varied for different SAR configurations. In parallel with the work on producing real-time high quality imagery has gone a program of research into automated image-understanding techniques. This work is now reaching the stage where reliable algorithms for several basic operations, including segmentation and change detections, exist in a form capable of processing continuous imagery at real time or near real-time rates. Provision has been made for the inclusion of these algorithms as postprocessing stages in the real-time SAR processor.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gordon C. Pryde, K. D. R. Beckett, L. M. Delves, Christopher John Oliver, and Richard Geoffrey White "Design of a real-time high-quality SAR processor", Proc. SPIE 2230, Algorithms for Synthetic Aperture Radar Imagery, (9 June 1994);

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