The feasibility of large scale optical proximity correction with a focus on mask manufacturability is demonstrated on the support and logic gates of a leading edge 64 Mb DRAM chip. Analysis of post reactive ion etch SEM data of the 500 - 600 nm, DUV exposed gates indicates two major contributors to across chip line width variation: first order proximity, that is, the minimum spacing to the nearest neighboring structure, and local area density or pattern loading. Data presented show a very long range (approximately equals 1 mm) impact of pattern density on post reactive ion etch line widths, favoring optical proximity correction approaches that are not based on biasing patterns to compensate for these effects. In this project, pattern density induced effects were alleviated by homogenizing the pattern loading across the chip to approximately 50% instead of biasing the gate structures to compensate for pattern density differences. Proximity induced effects were compensated for with a one- dimensional, single parameter (distance to nearest neighbor), four bucket proximity correction routine with a strong focus on mask manufacturability. Even though the unbiased 64 Mb DRAM gate level challenges mask makers with 480 MB of MEBES data, the optical proximity corrected mask posed no substantial post-processing, writing, or inspection problems in IBM's Burlington, Vermont maskhouse. A very significant 80% reduction in post reactive ion etch across chip line width variation was achieved with this corrected mask.