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15 September 1995 Development and production integration of a planarized AlCu interconnect process for submicron CMOS
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Abstract
A planarized aluminum alloy interconnect has been developed as an alternative to tungsten plugs for a 0.65 (mu) CMOS technology. Contact resistance can increase with either an inadequate RF sputter clean or titanium that is too thin to reduce the native oxide. Diffusion barrier results show that a minimum amount of titanium nitride, whether deposited conventionally or with collimation, is necessary for low junction leakage and good sort yield. Stacked contacts and vias are supported while via resistance and defect density are improved. Electrical bridging due to silicon residues from AlSiCu can be minimized with metal overetching, but not to the extent of AlCu. Sidewall pitting was observed to be due to galvanic corrosion from copper precipitate formation. Overall yield has been improved along with decreased wafer cost compared to conventional tungsten plug technology.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kevin C. Brown, Rodney Hill, Krishna Reddy, and Kamesh Gadepally "Development and production integration of a planarized AlCu interconnect process for submicron CMOS", Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); https://doi.org/10.1117/12.221137
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