Translator Disclaimer
15 September 1995 Latch-up temperature dependence of majority carrier guard structures up to 250-degrees C
Author Affiliations +
The purpose of this work was to investigate the latch-up temperature dependence of majority carrier guard structures with the goal to find design rules for latch-up free high temperature operation of a CMOS- ASIC. Measurements up to 250 degree(s)C show an enhanced latch-up resistance of majority carrier guards compared to conventional electrode placement. With increasing temperature holding voltage and current decrease for both types. The test devices have also been simulated using 2D FEM device simulation. For majority carrier guard structures it is essential to use Fermi-Dirac-statistics instead of Boltzmann-statistics and a mobility model which accounts for carrier-carrier scattering in order to get accurate simulation results. In a further step the simulations were used to predict the necessary guard width for holding voltages higher than 5V to gain absolutely latch-up free operation at 250 degree(s)C. The results can be exploited for the design of temperature resistant, latch- up free CMOS circuits. The work is relevant for an ongoing effort to make use of junction isolated CMOS technology for temperature resistant electronics up to 250 degree(s)C.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dirk Uffmann, Jens Stemmer, Hans-Ulrich Schroeder, Joerg Ackermann, and Jochen Aderhold "Latch-up temperature dependence of majority carrier guard structures up to 250-degrees C", Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995);


Low-noise SOI Hall devices
Proceedings of SPIE (May 08 2003)
Noise in carbon nanotube electronics
Proceedings of SPIE (May 23 2005)

Back to Top