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15 September 1995 Prediction of 0.18 um CMOS technology performance using tuned device simulation
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For the design of a scaled CMOS technology, it becomes necessary to use predictive device simulation to improve MOSFET design and reduce the design cycle time. The results of a simulation study which is carried out to predict the performance of N and P channel MOSFETs with a physical gate length (Lg) of 0.18 micrometers are reported in this paper. The performance of the MOSFETs is estimated using a performance Figure of Merit (FOM[1]) calculated from their simulated I-V characteristics. This study is used to identify particular improvements to an existing 0.25 micrometers , 2.5 V, 60 A technology [2] so as to meet the FOM target at a 0.18 micrometers , 1.5 V, 36 A technology node.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mahalingam Nandakumar, Mark Rodder, and Ih-Chin Chen "Prediction of 0.18 um CMOS technology performance using tuned device simulation", Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995);

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