Camcorders record motion video while electronic still cameras and computer cameras capture still images. Most camcorders are NTSC resolution, analog-based systems. A megapixel progressive scan motion and photographic still system is described in this paper which uses a high-resolution color CCD imager and the analog signal processing in Kodak Digital ScienceTM KASP series integrated circuits. For maintaining the 30 frames per second (fps) the sensor is clocked out at 37.5 MHz. The video output from a CCD sensor is in the shape of a high-frequency digital clock whose reset pedestal is embedded with KTC noise. Hence a correlated double sample and hold (CDS/H) circuit can give the difference between the reset pedestal and the video for every pixel and thus eliminate the KTC noise and 1/f noise. Every camera using a CCD sensor will have a CDS/H. Most cameras implement CDS/H at 40 MHz in the form of a filter or use general purpose track and hold amplifiers. Both options are bulky, expensive, and power hungry. Kodak has developed a monolithic 40 MHz analog signal processor (KASP-140G) with CDS/H using QuickTile standard cell architecture of Tektronix, Inc., using the Quickic tool set and the TSPICE analog circuit modeling tools. The paper describes the high-resolution progressive scan sensor, data rate speed issues, and present implementation methodologies of CDS/H at 40 MHz and compares the power, performance and cost savings by using KASP-140G. Kodak has designed four different analog signal processing chips with varying levels of power consumption and speed for analog signal processing of video output of CCD sensors. The analog application specific integrated circuits have been characterized for noise, clock feedthrough, acquisition time, linearity, variable gain, line rate clamp, black muxing, affect of temperature variation on chip performance, and droop. The ASP chips have met their design specifications.