Image processing using simplified Kohonen network

Hiroyuki Araki; Hikaru Fukumoto; Tadashi Ae

doi:10.1117/12.234653

5 March 1996 Image processing using simplified Kohonen network

Hiroyuki Araki, Hikaru Fukumoto, Tadashi Ae

Proceedings Volume 2661, Real-Time Imaging; (1996) https://doi.org/10.1117/12.234653
Event: Electronic Imaging: Science and Technology, 1996, San Jose, CA, United States

Abstract

We have designed a neuro-chip for Kohonen learning vector quantization (LVQ) algorithm, and fabricated it by gate-arrays, which includes 12 neurons/chip. We proposed a simplified version for Kohonen LVQ algorithm, because the gate-array restricts the number of transistors. Moreover, the fixed-point calculation is inevitable in neuro-chip. In this paper we demonstrate a good performance of our chip, which is used for bit-pattern image processing. For real-time systems learning can be done in real-time as well as i/o response. The neuro- chip can execute learning procedure (actually, Kohonen LVQ algorithm) in real-time. The first-version chip (already realized) can execute 32 bit patterns, but the second version will be enlarged to 256 bit pattern processing. The neurons become as much as chips are connected to a bus. The demonstration board using the first-version chips includes four chips, i.e., 48 neurons, which corresponds to 48 patterns recognition.

Citation Download Citation

Hiroyuki Araki, Hikaru Fukumoto, and Tadashi Ae "Image processing using simplified Kohonen network", Proc. SPIE 2661, Real-Time Imaging, (5 March 1996); https://doi.org/10.1117/12.234653

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