Tungsten plug contact and via integration for subhalf-micron technology

Harianto Wong; Chetlur S. Sreekanth; Lap Hung Chan

doi:10.1117/12.250886

13 September 1996 Tungsten plug contact and via integration for subhalf-micron technology

Harianto Wong, Chetlur S. Sreekanth, Lap Hung Chan

Proceedings Volume 2875, Microelectronic Device and Multilevel Interconnection Technology II; (1996) https://doi.org/10.1117/12.250886
Event: Microelectronic Manufacturing 1996, 1996, Austin, TX, United States

Abstract

Tungsten plug technology has been used extensively for multilevel interconnect in sub-half-micron semiconductor processes. The major issue encountered in tungsten plug integration is contact resistance especially to the p+ Si area and via resistance. In this study, investigations were carried out on several aspects of contact cleaning, plug implant, and barrier metal deposition. The test vehicle utilized is in-house logic test chip with 0.35 micrometers design rule. Contact resistance of tungsten plug was found to be strongly correlated with contact cleaning, plug implant and Ti deposition thickness. Ar sputter clean was shown to have detrimental effect towards contact and via resistances. Plug implant was shown to be a necessary step for p+ contact resistance control. Thicker Ti deposition was also shown to be crucial in improving contact resistance.

Citation Download Citation

Harianto Wong, Chetlur S. Sreekanth, and Lap Hung Chan "Tungsten plug contact and via integration for subhalf-micron technology", Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); https://doi.org/10.1117/12.250886

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