Efficiency analysis of mask fabrication with 1-Gb-DRAM storage node layer

Oscar Han; Byeong-Chan Kim; Hong-Bae Park; In-Seok Lee

doi:10.1117/12.262827

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27 December 1996 Efficiency analysis of mask fabrication with 1-Gb-DRAM storage node layer

Oscar Han, Byeong-Chan Kim, Hong-Bae Park, In-Seok Lee

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Proceedings Volume 2884, 16th Annual BACUS Symposium on Photomask Technology and Management; (1996) https://doi.org/10.1117/12.262827
Event: 16th Annual BACUS Symposium on Photomask Technology and Management, 1996, Redwood City, CA, United States

Abstract

Edge rounding effect and line pattern length shrink (pattern edge pull-back) are serious phenomena in nanometer optical lithography. Serif and opaque dummy patterns are typically used for optical proximity effect correction in R&D stages. In mass-production of next generation DRAM, the mask yield should be decreased by using these associated patterns. It comes mainly from small pattern defects which violate the design rule. Unfortunately it is difficult to detect these defects with a recently developed inspection system. Also mask fabrication induced defects are linked to the resolving power of inspection systems. In this work, we present efficiency analysis of mask fabrication process for storage node layer of a 1 Gb DRAM developed by using several types of optical proximity effect correction methods which are used to reduce corner rounding effect and edge pull-back for enhancing storage area.

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Oscar Han, Byeong-Chan Kim, Hong-Bae Park, and In-Seok Lee "Efficiency analysis of mask fabrication with 1-Gb-DRAM storage node layer", Proc. SPIE 2884, 16th Annual BACUS Symposium on Photomask Technology and Management, (27 December 1996); https://doi.org/10.1117/12.262827

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