Performance evaluation of FPGA implementations of high-speed addition algorithms

William W.H. Yu; Shanzhen Xing

doi:10.1117/12.255826

21 October 1996 Performance evaluation of FPGA implementations of high-speed addition algorithms

William W.H. Yu, Shanzhen Xing

Proceedings Volume 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic; (1996) https://doi.org/10.1117/12.255826
Event: Photonics East '96, 1996, Boston, MA, United States

Abstract

Driven by the excellent properties of FPGAs and the need for high-performance and flexible computing machines, interest in FPGA-based computing machines has increased dramatically. Fixed-point adders are essential building blocks of any computing systems. In this work, various high-speed addition algorithms are implemented in FPGAs devices, and their performance is evaluated with the objective of finding and developing the most appropriate addition algorithms for implementing in FPGAs, and laying the ground-work for evaluating and constructing FPGA-based computing machines. The results demonstrate that the performance of adders built with the FPGAs dedicated carry logic combined with some other addition algorithms will be greatly improved, especially for larger adders.

Citation Download Citation

William W.H. Yu and Shanzhen Xing "Performance evaluation of FPGA implementations of high-speed addition algorithms", Proc. SPIE 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (21 October 1996); https://doi.org/10.1117/12.255826

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