Three-step search motion estimation chip for MPEG-2 applications

You-Ming Chiu; Liang-Gee Chen; Yung-Ping Lee; Chung-Wei Ku

doi:10.1117/12.251314

16 September 1996 Three-step search motion estimation chip for MPEG-2 applications

You-Ming Chiu, Liang-Gee Chen, Yung-Ping Lee, Chung-Wei Ku

Proceedings Volume 2952, Digital Compression Technologies and Systems for Video Communications; (1996) https://doi.org/10.1117/12.251314
Event: Advanced Imaging and Network Technologies, 1996, Berlin, Germany

Abstract

In this paper, a hardware implementation of a 9-PE architecture for three-step search block-matching motion estimation algorithm is proposed. With intelligent data arrangement and memory configuration, the proposed architecture can reach the requirements of low costs, high speed, and low memory bandwidth. With 0.8 micrometer CMOS technology, the proposed chip requires a die size of 6.90 by 5.98 mm and is able to operate at a clock rate more than 50 MHz.

Citation Download Citation

You-Ming Chiu, Liang-Gee Chen, Yung-Ping Lee, and Chung-Wei Ku "Three-step search motion estimation chip for MPEG-2 applications", Proc. SPIE 2952, Digital Compression Technologies and Systems for Video Communications, (16 September 1996); https://doi.org/10.1117/12.251314

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