You have requested a machine translation of selected content from our databases. This functionality is provided solely for your convenience and is in no way intended to replace human translation. Neither SPIE nor the owners and publishers of the content make, and they explicitly disclaim, any express or implied representations or warranties of any kind, including, without limitation, representations and warranties as to the functionality of the translation feature or the accuracy or completeness of the translations.
Translations are not retained in our system. Your use of this feature and the translations is subject to all use restrictions contained in the Terms and Conditions of Use of the SPIE website.
27 December 1996Noise degradation and fault tolerance in annealed binary-phase hologram interconnections
Binary, computer-generated phase holograms can be displayed on a ferroelectric liquid crystal over silicon spatial light modulator to give a high-speed switchable interconnection element. However, these devices are prone to fabrication defects, including non-operational pixels, variations in the liquid crystal cell thickness and warping of the silicon backplane. We investigate the effects of these fabrication faults on hologram efficiency by modelling them in software, and test the ability of the iterative design technique to compensate for such defects. Evidence of back-plane and cell thickness faults in 256 by 256 pixel binary FLC over silicon SLMs is presented and discussed. A projected optical design scheme that removes the requirement for the mapping of defects on a particular SLM is outlined.
The alert did not successfully save. Please try again later.
Patrick J. Smith, Sergei Samus, William J. Hossack, David G. Vass, "Noise degradation and fault tolerance in annealed binary-phase hologram interconnections," Proc. SPIE 2969, Second International Conference on Optical Information Processing, (27 December 1996); https://doi.org/10.1117/12.262601