Versatile processor arrays based on segmented optical buses

Yueming Li; Si Qing Zheng; Xiangyang Yang

doi:10.1117/12.271099

Translator Disclaimer

4 April 1997 Versatile processor arrays based on segmented optical buses

Yueming Li, Si Qing Zheng, Xiangyang Yang

Author Affiliations +

Proceedings Volume 3005, Optoelectronic Interconnects and Packaging IV; (1997) https://doi.org/10.1117/12.271099
Event: Photonics West '97, 1997, San Jose, CA, United States

Abstract

We explore the potential of using optical waveguides and switches to build high performance parallel processing systems by introducing a new class of parallel computing architectures. This class of architectures are based on a special kind of reconfigurable buses called segmented buses. A segmented bus is a bus that can be dynamically partitioned into segments, called sub-buses, under program control. Such a bus can be used as a basic building block for constructing powerful parallel architectures. We show that parallel architectures based on segmented buses are versatile by embedding parallel communication patterns supported by a wide variety of networks such as linear array, ring, complete binary tree, X-tree, mesh-of-trees, multidimensional mesh, torus, multigrid and pyramid into segmented bus based architectures, and show that all these networks can be simulated with small slowdown factors.

Citation Download Citation

Yueming Li, Si Qing Zheng, and Xiangyang Yang "Versatile processor arrays based on segmented optical buses", Proc. SPIE 3005, Optoelectronic Interconnects and Packaging IV, (4 April 1997); https://doi.org/10.1117/12.271099

ACCESS THE FULL ARTICLE