Processing Display System Architectures

L. Howard Roberts; Michael Shantz

doi:10.1117/12.932609

23 July 1982 Processing Display System Architectures

L. Howard Roberts, Michael Shantz

Proceedings Volume 0301, Design of Digital Image Processing Systems; (1982) https://doi.org/10.1117/12.932609
Event: 25th Annual Technical Symposium, 1981, San Diego, United States

Abstract

Recent advances in the design of image processing and display equipment have occurred in two key areas, namely, data flow architectures and pipeline array processor architectures. Data flow involves the use of high speed data interfaces to the display processor, a flexible internal bus architecture, and efficient access to display processor memories. Image processing power is achieved through the use of pipeline processors rather than high-speed, large address-space, integral CPUs. Hardware constraints impact the design of algorithms which take advantage of the 70 nanosecond pixel rates and the computational power of the pipeline processors. The DeAnza Systems IP 8500 and IP 1172 image processing display systems exemplify architectural advances in data flow and pipeline processor architectures.

Citation Download Citation

L. Howard Roberts and Michael Shantz "Processing Display System Architectures", Proc. SPIE 0301, Design of Digital Image Processing Systems, (23 July 1982); https://doi.org/10.1117/12.932609

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