Design and tuning of FPGA implementations of neural networks

Peter J. C. Clare; J. W. Gulley; Duncan Hickman; Moira I. Smith

doi:10.1117/12.277097

23 June 1997 Design and tuning of FPGA implementations of neural networks

Peter J. C. Clare, J. W. Gulley, Duncan Hickman, Moira I. Smith

Proceedings Volume 3069, Automatic Target Recognition VII; (1997) https://doi.org/10.1117/12.277097
Event: AeroSense '97, 1997, Orlando, FL, United States

Abstract

Artificial neural network (ANN) algorithms are applicable in a variety of roles for image processing in infrared search and track (IRST) systems. Achieving a high throughput is a key objective in developing ANNs for processing large numbers of pixels at high frame rates. Previous work has investigated the use of a neural core supported by configurable logic to achieve a versatile technology applicable to a variety of systems. The implementation of multi-layer perceptron (MLP) ANNs, using field programmable gate array (FPGA) technology to ensure upgradability and reconfigurability, is the focus of this research. Approximations to the MLP algorithms are needed to ensure that a high throughput can be achieved with a sufficiently low gate count.

Citation Download Citation

Peter J. C. Clare, J. W. Gulley, Duncan Hickman, and Moira I. Smith "Design and tuning of FPGA implementations of neural networks", Proc. SPIE 3069, Automatic Target Recognition VII, (23 June 1997); https://doi.org/10.1117/12.277097

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