Developments of optimum flip-chip bonding process

Dong Hyeon Jang; Sa Yoon Kang; Y. M. Lee; S. Y. Oh

doi:10.1117/12.280566

18 August 1997 Developments of optimum flip-chip bonding process

Dong Hyeon Jang, Sa Yoon Kang, Y. M. Lee, S. Y. Oh

Proceedings Volume 3184, Microelectronic Packaging and Laser Processing; (1997) https://doi.org/10.1117/12.280566
Event: ISMA '97 International Symposium on Microelectronics and Assembly, 1997, Singapore, Singapore

Abstract

Flip-chip soldering is the critical technology for solving the current issues of electronic packaging industries that require the high I/O's. In order to increase the manufacturing ability of flip-chip technology, however, yield and reliability tissues should overcome. In this study, optimum flip-chip bonding process has been developed by using the test chips that had the electroplated solder bumps. Test chips are composed of three different types that are i) peripheral array pad chip, ii) peripheral array pad chip, and iii) area array pad chip. Each test chip has the daisy chain to consider the effect of reliability test. The electrical resistance was measured before and after reliability test. Based on these measurement, failure mode resulted from the moisture absorption was studied using scanning acoustic microscope. To achieve an optimum reflow profile of solder bump, correct temperature profile was set up with respect to the resin base flux. Different bonding forces were tested. Four underfill encapsulants were evaluated for minimum voids that caused the severe defects after reliability test. Also, the gap heights were measured with respect to applied bonding force after underfill was performed. Results from the moisture absorption and thermal cycling were discussed for flip-chip bonding on BT-resin substrates. The test vehicles using flip-chip technology have passed moisture preconditioning and temperature cycling tests.

Citation Download Citation

Dong Hyeon Jang, Sa Yoon Kang, Y. M. Lee, and S. Y. Oh "Developments of optimum flip-chip bonding process", Proc. SPIE 3184, Microelectronic Packaging and Laser Processing, (18 August 1997); https://doi.org/10.1117/12.280566

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