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5 September 1997 IC-compatible fabrication of through-wafer conductive vias
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Proceedings Volume 3223, Micromachining and Microfabrication Process Technology III; (1997)
Event: Micromachining and Microfabrication, 1997, Austin, TX, United States
A novel process for the fabrication of high aspect-ratio high density through-wafer conductive vias is presented. This IC compatible post-processing technology is based on the use of silicon fast anisotropic plasma etching. It overcomes the inherent size or process limitations of previously known methods based on anisotropic chemical etching or laser drilling. The simple process (4 photolithographic steps) includes: (1) Realization of through-wafer holes by fast silicon etching in a low temperature inductively coupled plasma. (2) Insulation of the through-hole walls by room temperature chemical vapor deposition of an organic polymer. (3) Metallization of the through-hole walls by sputtering and evaporation. (4) Insulator dry etching and metal wet etching with a dry film photoresist mask that provides the necessary tenting capability over the through-holes. The process feasibility has been successfully demonstrated with a test design integrated on 100 mm 380 micrometer thick silicon wafers. The through-wafer vias, with a pitch of 350 micrometer and an average density of 100 (DOT) cm-2, have an electrical resistance of 2 (Omega) and a parasitic capacitance lower than 1 pF.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jean Gobet, Jean-Phillipe Thiebaud, Francois Crevoisier, and Jean-Marc Moret "IC-compatible fabrication of through-wafer conductive vias", Proc. SPIE 3223, Micromachining and Microfabrication Process Technology III, (5 September 1997);

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