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5 May 1998 VLSI photonic smart-pixel array for I/O system architectures
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Optoelectronic integrated circuits (OEICs) containing 32 X 32 arrays of smart pixels on 512 micrometers centers are under development for use in high density input/output (I/O) applications. Each smart pixel will comprise a monolithically integrated detector, a CMOS circuit, and a flip-chip bonded, oxide confined GaAs/AlGaAs vertical cavity surface emitting laser (VCSEL). The CMOS circuit will include a receiver, a digital section, and a laser driver. The digital sections of adjacent pixels will be connected in series to provide high speed 1D and 2D optical I/O into the smart pixel array. This low-power architecture will combine functionality, testability, and electrical/optical access in a single compact circuit. The OEIC will serve as a robust optoelectronic device and also as a test-bed upon which to develop techniques for flip-chip bonding the GaAs/AlGaAs VCSELs onto CMOS circuitry. The smart pixel device will operate at a speed of up to 1 GHz. The 32 X 32 array will consume < 10 W.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christine T. Travers, John M. Hessenbruch, Jongwoo Kim, Richard V. Stone, Peter S. Guilfoyle, and Fouad E. Kiamilev "VLSI photonic smart-pixel array for I/O system architectures", Proc. SPIE 3288, Optoelectronic Interconnects V, (5 May 1998);

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