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26 March 1998 Mapping of video decoder software on a VLIW DSP multiprocessor
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Proceedings Volume 3311, Multimedia Hardware Architectures 1998; (1998)
Event: Photonics West '98 Electronic Imaging, 1998, San Jose, CA, United States
When implementing today's video compression standards on programmable processors, it is essential to optimize the algorithms with respect to the underlying hardware. As an example, the core decoder functions of the H.263 hybrid coding scheme were implemented on a SIMD controlled processor with four parallel VLIW data paths, the HiPAR-DSP. The decoder tasks were implemented employing local memory, parallelization on several levels, and data statistics. Special effort was paid on the computation intensive tasks IDCT, and motion compensated frame reconstruction. To speed up the IDCT computation, a data dependent approach was chosen, which distinguishes different block types. The determination of IDCT block type could be parallelized together with other tasks, thus no additional overhead is required. Frame reconstruction mainly benefits from data parallel operations and transparent DMA transfers to and from external memory.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Achim Freimann, Thomas Brune, and Peter Pirsch "Mapping of video decoder software on a VLIW DSP multiprocessor", Proc. SPIE 3311, Multimedia Hardware Architectures 1998, (26 March 1998);


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