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26 March 1998 Parallelism analysis of the memory system in single-chip VLIW video signal processors
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Proceedings Volume 3311, Multimedia Hardware Architectures 1998; (1998)
Event: Photonics West '98 Electronic Imaging, 1998, San Jose, CA, United States
This paper presents a design study of the memory system for a very long instruction word (VLIW) video signal processor (VSP). The gap between memory and modern processors is continuously becoming wider and wider, and thus memory systems have been a subject of active research for a long time.However, memory issues in VLIW machines have not yet been addressed. Real-time video signal processing requires a fast memory with high-bandwidth and high-connectivity. Efficient memory system design is particularly important for VSPs that combine significant amounts of memory on-chip with the processor, which we expect to become common in the next generation of VSPs. In this paper we use trace-driven methodology to analyze the parallelism, especially that of memory operations, in video applications. With a scheduling range of up to ne billion operations, we analyzed large traces of several real applications including H.263, MPEG2 and MPEG4. We found that even with a conservative configuration the average speedup is more than 8.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Zhao Wu and Wayne H. Wolf "Parallelism analysis of the memory system in single-chip VLIW video signal processors", Proc. SPIE 3311, Multimedia Hardware Architectures 1998, (26 March 1998);

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