Holographic memory design for a petaflop superconducting computer architecture

Ernest Chuang; Wenhai Liu; Demetri Psaltis

doi:10.1117/12.308959

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22 May 1998 Holographic memory design for a petaflop superconducting computer architecture

Ernest Chuang, Wenhai Liu, Demetri Psaltis

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Proceedings Volume 3490, Optics in Computing '98; (1998) https://doi.org/10.1117/12.308959
Event: Optics in Computing '98, 1998, Bruges, Belgium

Abstract

We will descrihe the role of holographic memorv in a current research effort 1 that seeks to combine ariuus advanced technologies to achieve petaflops scale computing within the next decade In addition to holographic memory. the petatlop architecture combines superconductor Rapid Single Flu-.: Quantum (RSFQ) logic. which can operate at I 00 GHz within a cryogenic cm ironmem with power consumption less than 'iO watts. a packet-switching optical network with a multi-le el strncture capable of providing interconnection among tens or thousands of pons '' ith latencies of only I 0 to 30 nanoseconds. Processor-In-Memory (PIM) technology. and a multithreaded hierarchical structure (see Figure I) to allow the processors to access a high capacitv memnrv vhile compensating for the latenc)· problem inherent in such a system.

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Ernest Chuang, Wenhai Liu, and Demetri Psaltis "Holographic memory design for a petaflop superconducting computer architecture", Proc. SPIE 3490, Optics in Computing '98, (22 May 1998); https://doi.org/10.1117/12.308959

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