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In order to continue scaling the gate to gate spacing in CMOS for higher packing density, the thickness of source/drain (S/D) spacer and the S/D junction depth (Xj) underneath the silicide film have to be scaled accordingly. Therefore silicided shallow junction with low diode leakage at S/D region has to be achieved. Silicide as diffusion source (SADS) is an attractive shallow function formation technology, because it is a relatively simple and low-cost technology compared to other shallow junction techniques, such as raised source/drain. In the SADS process, first the self-aligned salicide is formed and followed by the S/D dopant implant into the silicided region. Subsequently low temperature annealing is performed to drive out the dopants from the silicide film and form shallow junctions. Since dopants diffuse fast in silicide, ideally the junction follows the silicide/silicon interface contour (including the any existing spiking region), which low diode leakage can be achieved. In this study, nMOS devices fabricated with CoSi2 SADS were compared with devices fabricated using the conventional cobalt silicided junction. The spacer thickness was varies from 350 Angstrom to 850 Angstrom. Different annealing conditions (temperature and time) used to drive As dopants out of the CoSi2 film were also studied. The advantages and problems associated with the SADS in a deep sub-micron process flow will be discussed. The key results from this study are as follows. (1) Initially Xj of SADS junction increases with the annealing temperature, and then it decreases as the temperature continues increasing. Significant dopant loss occurred at high annealing temperature. (2) NMOS devices fabricated using SADS showed much better short channel characteristics compared to the conventional devices especially when the thin spacer was used. (3) Less inverse short channel effect was shown in SADS devices, which improved the variation of drive current with gate length. (4) SADS devices showed slight degradation in drive current, which was caused by the worse gate-depletion in these devices. (5) The best annealing condition for low diode leakage in the SADS junction was identified in this study. However, even in the best case, the diode leakage is an order of magnitude higher than the conventional silicided shallow junction. The drawbacks of SADS in deep sub-micron transistor design were identified and discussed.
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