Sub-50-nm PtSi Schottky source/drain MOSFETs

Chinlee Wang; John P. Snyder; John R. Tucker

doi:10.1117/12.323975

4 September 1998 Sub-50-nm PtSi Schottky source/drain MOSFETs

Chinlee Wang, John P. Snyder, John R. Tucker

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323975
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

PtSi source/drain Schottky barrier MOSFETs have been fabricated at sub-50-nm channel lengths with 19-angstrom gate oxide. These p-channel devices employ gate-induced field emission through the PtSi approximately 0.2-eV hole barrier to achieve current drives of approximately 200 (mu) A/micrometer at supply voltage of 1.0 V. Delay times measured by the CV/I metric extends scaling trends of conventional p-MOSFETs to approximately 2 - 3 ps. Thermal emission over the low Schottky barrier limits on/off currents to approximately 25 - 50 in undoped devices at 300 K, while ratios of approximately 10⁷ are measured at 77 K. On/off ratios at room temperature can be improved to approximately 10³ by implanting a thin layer of fully-depleted donors beneath the active region or use of ultra-thin SOI substrates.

Citation Download Citation

Chinlee Wang, John P. Snyder, and John R. Tucker "Sub-50-nm PtSi Schottky source/drain MOSFETs", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323975

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