Influence of silicon surface integrity on device yield

Yasuhiro Kimura; Hideki Naruoka; Morihiko Kume; Toshiharu Katayama; Hidekazu Yamamoto; Yoji Mashiko

doi:10.1117/12.324374

Translator Disclaimer

28 August 1998 Influence of silicon surface integrity on device yield

Yasuhiro Kimura, Hideki Naruoka, Morihiko Kume, Toshiharu Katayama, Hidekazu Yamamoto, Yoji Mashiko

Author Affiliations +

Proceedings Volume 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV; (1998) https://doi.org/10.1117/12.324374
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

We have investigated the influence of silicon surface integrity (SSI) on LSI device characteristics and yield. It was found that SSI spoiling during the wafer shaping process causes the reduction of gate oxide integrity (GOI), resulting in poor yield of LSIs. We demonstrated that some analysis techniques, such as long-time SC-1 cleaning, the combination of Cu decoration method and SEM observation and optical shallow defect analyzer are effective for evaluation of SSI. By Cu decoration and SEM observation, many small pits of about 0.03 micrometers were observed at GOI failure points. In addition, a model for pit generation was also established in this study. It is thought that Cu ions from contamination takes electrons from activated Si surface in pure water, and oxidized the Si surface partly. The Cu was removed by SC-1 final cleaning, and only pits remain on the Si wafer surface. The pits were primary cause of GOI failure and abnormal LPD increase.

Citation Download Citation

Yasuhiro Kimura, Hideki Naruoka, Morihiko Kume, Toshiharu Katayama, Hidekazu Yamamoto, and Yoji Mashiko "Influence of silicon surface integrity on device yield", Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); https://doi.org/10.1117/12.324374

ACCESS THE FULL ARTICLE