Translator Disclaimer
24 May 1999 Reconfigurable parallel processor for noise suppression
Author Affiliations +
Digital images corrupted with noise regularly require different filtering techniques to optimally correct the image. Software provides convenience for implementing a variety of different filters, but suffers a speed penalty due to its serial nature of the filter calculations. In converse fashion, implementation using ASIC technology allows for a speed advantage due to parallel processing but at the cost of increased hardware overhead for implementing a variety of filters individually. Advances in Field Programmable Gate Array (FPGA) technology offers a middle ground in which the speed advantages of an ASIC and the reprogrammable aspect of a general purpose conventional CPU or DSP software approach are combined. In this paper, we present an FPGA-based, reconfigurable system, that can perform an assortment of noise filtering algorithms using the same hardware. Implementation of Gaussian and salt-and-pepper noise are evaluated for this system.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Cuviello, Philip P. Dang, and Paul M. Chau "Reconfigurable parallel processor for noise suppression", Proc. SPIE 3663, Medical Imaging 1999: Image Perception and Performance, (24 May 1999);


Back to Top