PN and SOI wafer flow process for stencil mask fabrication

Joerg Butschke; Albrecht Ehrmann; Ernst Haugeneder; Mathias Irmscher; Rainer Kaesmaier; Karl Kragler; Florian Letzkus; Hans Loeschner; Josef Mathuni; Ivo W. Rangelow; Carsten Reuter; Feng Shi; Reinhard Springer

doi:10.1117/12.346224

Translator Disclaimer

23 April 1999 PN and SOI wafer flow process for stencil mask fabrication

Joerg Butschke, Albrecht Ehrmann, Ernst Haugeneder, Mathias Irmscher, Rainer Kaesmaier, Karl Kragler, Florian Letzkus, Hans Loeschner, Josef Mathuni, Ivo W. Rangelow, Carsten Reuter, Feng Shi, Reinhard Springer

Author Affiliations +

Proceedings Volume 3665, 15th European Conference on Mask Technology for Integrated Circuits and Microcomponents '98; (1999) https://doi.org/10.1117/12.346224
Event: 15th European Conference on Mask Technology for Integrated Circuits and Micro-Components, 1998, Munich, Germany

Abstract

Two process flows for the fabrication of stencil masks have been developed. The PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6 inch Si base wafers with 3 micrometers membrane thickness and a membrane diameter between 120 mm and 126 mm were fabricated. The membrane stress depending on the material property and doping level has been determined. First metrology measurements have been carried out.

Citation Download Citation

Joerg Butschke, Albrecht Ehrmann, Ernst Haugeneder, Mathias Irmscher, Rainer Kaesmaier, Karl Kragler, Florian Letzkus, Hans Loeschner, Josef Mathuni, Ivo W. Rangelow, Carsten Reuter, Feng Shi, and Reinhard Springer "PN and SOI wafer flow process for stencil mask fabrication", Proc. SPIE 3665, 15th European Conference on Mask Technology for Integrated Circuits and Microcomponents '98, (23 April 1999); https://doi.org/10.1117/12.346224

ACCESS THE FULL ARTICLE