Scaling the gate dielectric

David J. Eaglesham

doi:10.1117/12.360539

1 September 1999 Scaling the gate dielectric

David J. Eaglesham

Proceedings Volume 3881, Microelectronic Device Technology III; (1999) https://doi.org/10.1117/12.360539
Event: Microelectronic Manufacturing '99, 1999, Santa Clara, CA, United States

Abstract

The gate dielectric is arguably the biggest challenge facing the physical scaling of the MOSFET. The alternatives to continued scaling of SiO₂ include radical departures from standard process flows and very challenging new materials issues. In the short term, the industry continues to pursue improvements to the reliability and tunneling performance of silicon-dioxide. New data on reliability suggests that SiO₂ as thin as 1.6nm may achieve acceptable reliability in the field. Beyond SiO₂, there is no material which has yet demonstrated comparable reliability or interface-state-density. The most promising approach involves using sandwiched high-k material, with thin SiO₂ at both interfaces. Either Ta₂O₅ or TiO₂ may be suitable in structures of this type.

Citation Download Citation

David J. Eaglesham "Scaling the gate dielectric", Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); https://doi.org/10.1117/12.360539

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