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1 September 1999 Stress-induced leakage currents of CMOS ULSI devices with shallow trench isolation
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Abstract
The correlation of MOSFET electrical characteristics to the levels of mechanical stress in STI structures used for the device manufacturing has been analyzed. The model of stress evolution during STI formation was developed based on the results of experimental measurements and computer simulations. Accordingly, STI processes creating different levels of stresses were designed and used to manufacture ULSI. Electrical parameters of a large variety of MOSFET devices were tested and weighted against the STI processes employed. This enabled the identification of the device leakage currents which resulted from high STI stress: the diode leakage dependent on isolation width, MOSFET standby currents dependent on active device width and gate bias, and the excessive leakage of field-edge-intensive devices. The first phenomenon was found to be associated with the incident of dislocations. The other kinds of leakage could reach critical levels even at moderate stress below the threshold for the onset of dislocation. According to the results of the device leakage characterization, critical stress states of STI structures can be readily monitored using conventional approaches of electrical testing. This provides an effective means for STI process and material integration and obtaining low stress dislocation-free structures.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ravi Sundaresan, Chock Hing Gan, and Igor V. Peidous "Stress-induced leakage currents of CMOS ULSI devices with shallow trench isolation", Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); https://doi.org/10.1117/12.360556
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