Merged CCD/SOI-CMOS technology

Vyshi Suntharalingam; Barry E. Burke; J. A. Burns; M. J. Cooper; Craig L. Keast

doi:10.1117/12.385466

15 May 2000 Merged CCD/SOI-CMOS technology

Vyshi Suntharalingam, Barry E. Burke, J. A. Burns, M. J. Cooper, Craig L. Keast

Proceedings Volume 3965, Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications; (2000) https://doi.org/10.1117/12.385466
Event: Electronic Imaging, 2000, San Jose, CA, United States

Abstract

In this paper we describe a new technology which fabricates CCDs and fully depleted silicon on insulator CMOS circuits on the same 150-mm silicon wafer. We present results from 7.5 X 7.5-micrometers ² and 15 X 15-micrometers ²-pixel imagers that are 512 X 512 frame transfer devices. The 7.5-micrometers -pixel device exhibits a charge handling capacity in excess of 100,000 electrons at 3.3 V and the 15-micrometers - pixel device exhibits a charge-transfer efficiency over 99.998%. In addition, we demonstrate functional SOI CMOS ring oscillators with delay of 47 ps/stage at 3.3 V and 68 ps/stage at 2 V.

Citation Download Citation

Vyshi Suntharalingam, Barry E. Burke, J. A. Burns, M. J. Cooper, and Craig L. Keast "Merged CCD/SOI-CMOS technology", Proc. SPIE 3965, Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications, (15 May 2000); https://doi.org/10.1117/12.385466

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