Reduction of wafer-scale error between DI and FI in multilevel metallization by adjusting edge detection method

Sang-Gil Bae; Young-Keun Kim; Ki-Yeop Park; Jin-Soo Kim; Won-Kyu Lee; S.W. Lee; Dai-Hoon Lee

doi:10.1117/12.386502

2 June 2000 Reduction of wafer-scale error between DI and FI in multilevel metallization by adjusting edge detection method

Sang-Gil Bae, Young-Keun Kim, Ki-Yeop Park, Jin-Soo Kim, Won-Kyu Lee, S.W. Lee, Dai-Hoon Lee

Author Affiliations +

Proceedings Volume 3998, Metrology, Inspection, and Process Control for Microlithography XIV; (2000) https://doi.org/10.1117/12.386502
Event: Microlithography 2000, 2000, Santa Clara, CA, United States

Abstract

As the integration density of VLSI device increases, the overlay accuracy in the photolithography becomes more and more important. In the sub-quarter micron technology, the registration budget is less than 70 nm. Registration error can be induced by the repeatability error of alignment sensor, mask fabrication error, tool induced shift, process induced shift, and so on. One of these misregistration error sources, overlay parameter difference between DI and FI, can cause significant damage to the device because, in most cases, overlay accuracy is checked only in the mask step. In this paper, we studied the relationship of the Edge Detection Algorithm (EDA) and the overlay mark structure to the wafer scale difference.

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Sang-Gil Bae, Young-Keun Kim, Ki-Yeop Park, Jin-Soo Kim, Won-Kyu Lee, S.W. Lee, and Dai-Hoon Lee "Reduction of wafer-scale error between DI and FI in multilevel metallization by adjusting edge detection method", Proc. SPIE 3998, Metrology, Inspection, and Process Control for Microlithography XIV, (2 June 2000); https://doi.org/10.1117/12.386502

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