Application of chromeless phase-shift masks to sub-100-nm SOI CMOS transistor fabrication

Michael Fritze; James M. Burns; Peter W. Wyatt; David K. Astolfi; T. Forte; Donna Yost; Paul Davis; Andrew V. Curtis; Douglas M. Preble; Susan G. Cann; Sandy Denault; Hua-Yu Liu; Joe C. Shaw; Neal T. Sullivan; Robert Brandom; Martin E. Mastovich

doi:10.1117/12.389028

5 July 2000 Application of chromeless phase-shift masks to sub-100-nm SOI CMOS transistor fabrication

Michael Fritze, James M. Burns, Peter W. Wyatt, David K. Astolfi, T. Forte, Donna Yost, Paul Davis, Andrew V. Curtis, Douglas M. Preble, Susan G. Cann, Sandy Denault, Hua-Yu Liu, Joe C. Shaw, Neal T. Sullivan, Robert Brandom, Martin E. Mastovich

Author Affiliations +

Proceedings Volume 4000, Optical Microlithography XIII; (2000) https://doi.org/10.1117/12.389028
Event: Microlithography 2000, 2000, Santa Clara, CA, United States

Abstract

This work looks at the application of chromeless phase-shift masks to sub-100 nm gatelength SOI transistor fabrication. The double-exposure technique of Numerical Technologies is extended to the chromeless-edge case. Two masks are used in this method. The first is a darkfield mask with chromeless edges defining the minimum geometry gates and the second is a binary blockout mask which also patterns the larger gate features. This approach provides considerably enhanced resolution performance compared with alternating aperture while still preserving good process latitudes. The chromeless mask fabrication approach is discussed. A simple, single step dry etch is used with no minimum geometry features, thus simplifying mask fabrication. We employed an 0.6 NA, DUV tool for this work together with commercially available resist and anti-reflection layers. Lithography results for k₁ factors down to 0.10 and 0.3 are presented. This corresponds to CDs of 40 nm and 125 nm on our Canon EX-4, 248nm stepper. Excellent pattern transfer into polysilicon was achieved using a high density plasma etch process producing gate features down to 25 nm linewidths. We discuss the application of this method to the fabrication of sub-100 nm gate-length fully-depleted SOI CMOS transistors. We have fabricated SOI CMOS transistors with excellent short channel behavior down to 50 nm physical gate lengths. This method enables the development of deep sub-100 nm gate length CMOS technologies using standard 248- nm exposure sources.

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Michael Fritze, James M. Burns, Peter W. Wyatt, David K. Astolfi, T. Forte, Donna Yost, Paul Davis, Andrew V. Curtis, Douglas M. Preble, Susan G. Cann, Sandy Denault, Hua-Yu Liu, Joe C. Shaw, Neal T. Sullivan, Robert Brandom, and Martin E. Mastovich "Application of chromeless phase-shift masks to sub-100-nm SOI CMOS transistor fabrication", Proc. SPIE 4000, Optical Microlithography XIII, (5 July 2000); https://doi.org/10.1117/12.389028

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