According to the SIA roadmap an overlay of 65nm is necessary for state of the art 0.18micrometers processes. To meet such tight requirements it is necessary to know the magnitude of all contributions, to understand possible interactions and to try to drive every individual overlay component to its ultimate lower limit. In this experimental study we evaluate the impact of different contributions on the overall overlay performance in a fab equipped exclusively with ASML step and scan systems. First we discuss the overlay performance of advanced step and scan systems in a mix and match scenario, focusing on single machine overlay, long term stability and multiple machine matching. We show that both distortion and stage differences between different tools are typically less than 22nm, justifying a multiple machine scenario without significant loss of overlay performance. In the next step, we discuss the impact of layer deposition and CMP. We include shallow trench isolation, tungsten-CMP as well as conventional aluminum wiring and copper-dual-damascene technology into our examinations. In particular, we discuss the pro's and con's of using a zero-layer-mark-approach, compared to an alignment on marks formed in certain layers for direct layer to layer alignment. Furthermore, we examine the performance of ASMLs 'through-the-lens' (TTL)-alignment system becomes as small as 6nm using TTL-alignment. For marks directly affected by CMP-processes technology impact can be controlled within 13nm. We show that, even in a scenario with multiple tools matched to each other, where alignment marks are directly affected by a CMP process step, and where the standard TTL alignment marks are directly affected by a CMP process step, and where the standard TTL alignment system is used, the overall overlay can be controlled within 60nm. Using the ATHENA alignment system, a further improvement is possible.