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12 July 2000 Development of a real-time Sensor Emulator System for hardware-in-the-loop testing
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Abstract
This paper describes the Sensor Emulator System developed at AMCOM using custom off the shelf image processing hardware combined with in-house designed interfaces to SGI Digital Video Port (DVP) input and output hardware. The system was designed to allow the emulation processing elements to be inserted in the image output path of the SGI computers currently being used in the Hardware-in-the-Loop (HWIL) facilities. This is accomplished by converting the SGI's DVP output to the emulator's input bus format, and after being processed, the output is converted back to DVP format. The images can then be input to in-house designed injector or projector interfaces. Sixteen bit images of 256 X 256 pixels, at frame rates of 800 Hz have been input, processed in parallel on 5 nodes, and output with this system. The system's processing elements are Matrox Genesis image processing boards. Each processing node consists of a Texas Instruments C80, a Matrox Neighborhood Operation Accelerator ASIC (NOA2) and a Matrox Video Interface ASIC (VIA). The NOA2 is a multiplier/accumulator (MAC) array capable of 32 simultaneous sum of products at 50 MHz. The VIA provides high- speed links between acquisition, processing and display devices by controlling multiple independent 32 bit wide busses. It controls the image acquisition and fan-out to the processing Nodes and output without adding overhead. The C80 provides the processing for sensor electronic functions such as gains, offsets, dead pixels, saturation, etc. This combination has the capability of processing large, high frame rate images in real time.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
James A. Buford Jr., Monty Offutt, and Terry M. Reynolds "Development of a real-time Sensor Emulator System for hardware-in-the-loop testing", Proc. SPIE 4027, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing V, (12 July 2000); https://doi.org/10.1117/12.391684
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