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19 July 2000 New approach to mask and wafer performance optimization for system-on-a-chip (SOC) devices
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Proceedings Volume 4066, Photomask and Next-Generation Lithography Mask Technology VII; (2000) https://doi.org/10.1117/12.392073
Event: Photomask and Next Generation Lithography Mask Technology VII, 2000, Kanagawa, Japan
Abstract
Detection of reticle CD errors appears to be one of the most critical challenges for low-k1 lithography, where CD accuracy, as mean-to-normal and mask error factor determine most of wafer CD budget. Measurements of reticle CDs are always a difficult process, as the mask manufacturer need to know the critical areas on the masks where he has to execute the measurements. This information is not generally available and if it is available, the number of measurements can be extremely large, in particular for system-on-a-chip devices with multiple critical number of measurements can be extremely large, in particular for system-on-a-chip devices with multiple critical areas resulting from the multiple electrical functions located on a chip. For these reasons, it becomes extremely interesting to execute the reticle CD metrology in a 'two-step' approach: first, detection of 'global' CD errors during the reticle inspection, followed by the second step, where the CD measurements will be executed only in those areas where the global CD error algorithm has detected errors large enough to affect wafer CD control. In this way, the among of CD measurements will be reduced to a manageable number and more important, measurements will be executed only in those area that have large errors. However, there is one critical concern in this approach, that is the capability of the 'global CD error' algorithm to accurately detect CD errors in areas with various chrome density as well as to detect CD errors of minimum 20 to 30nm which represent the specification of a good reticle for low-k1 lithography. In this paper, we report on a layout design with programmed CD errors and on the first result of applying the global CD error algorithm to detect these errors. The layout with programmed CD errors, is a multi-die per reticle case with several levels of CD errors, from global shifts in mean CD, to errors programed in a regular or in a random array inside the reticle active area. This design stresses the measurement algorithm as the programmed CD errors are combined with chrome density varying across the die, by a factor of 1 to 2.5X. One of the useful features of the proposed algorithm, detection of large CD fingerprint errors on the reticle, has been demonstrated in this work.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gidon Gottlib, Yair Eran, Shirley Hemar, Amikam Sade, Wolfgang Staud, Mircea V. Dusa, and Steve Warila "New approach to mask and wafer performance optimization for system-on-a-chip (SOC) devices", Proc. SPIE 4066, Photomask and Next-Generation Lithography Mask Technology VII, (19 July 2000); https://doi.org/10.1117/12.392073
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