Fast search block-matching motion estimation algorithm using FPGA

Vera Ying Y. Chung; Man To Wong; Neil W. Bergmann

doi:10.1117/12.386693

30 May 2000 Fast search block-matching motion estimation algorithm using FPGA

Vera Ying Y. Chung, Man To Wong, Neil W. Bergmann

Proceedings Volume 4067, Visual Communications and Image Processing 2000; (2000) https://doi.org/10.1117/12.386693
Event: Visual Communications and Image Processing 2000, 2000, Perth, Australia

Abstract

Many fast search block-matching motion estimation (BMME) algorithms have been developed in order to minimize the search positions and speed up the computation but they do not consider how they can be effectively implemented by hardware. In this paper, we propose a new regular fast search block-matching motion estimation algorithm named Two Step Search (2SS). The 2SS BMME will then be implemented by 8 Xilinx XC6216 fine-grain, sea-of-gate FPGA chips. The experimental and simulation results shows that it can have better algorithmic performance and can be implemented by FPGA chips very cost-effectively for video compression applications. Also, the 30 frames per second real time 2SS BMME video compression can be obtained by using eight Xilinx XC6216 FPGAs.

Citation Download Citation

Vera Ying Y. Chung, Man To Wong, and Neil W. Bergmann "Fast search block-matching motion estimation algorithm using FPGA", Proc. SPIE 4067, Visual Communications and Image Processing 2000, (30 May 2000); https://doi.org/10.1117/12.386693

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