Paper
18 August 2000 Planarization approaches to via-first dual-damascene processing
Edward K. Pavelchek, Marjorie Cernigliaro, Peter Trefonas III, Manuel doCanto
Author Affiliations +
Abstract
Via fill and intervia coverage of AR5 and AR7 anti-reflectants were measured for 608nm deep vias in thermal oxide. Fitting functions were found which gave god agreement with experimental data. The most important factors were AR thickness, via duty ratio and via width. The importance of these factors was different for via fill and intervia coverage, and for AR5 and AR7. AR7 was found to fill a range of vias to a depth of 25 percent to 50 percent, suitable for a partial planarization approach to dual damascene fabrication. Planarization was shown to be relatively insensitive to several coat process variations, but sensitive to solution surface tension.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Edward K. Pavelchek, Marjorie Cernigliaro, Peter Trefonas III, and Manuel doCanto "Planarization approaches to via-first dual-damascene processing", Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); https://doi.org/10.1117/12.395723
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KEYWORDS
Dielectrics

Transistors

Voltage controlled current source

Logic

Manufacturing

Copper

Metals

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